The Internet and advanced applications require higher performance from microprocessors, central processing units CPUs, or processors (“processors”) in computing systems. These systems require processors to process instructions, access resources, and send/receive data at high speeds. Along with processors, computing systems typically include memory systems, memory caches, data/system busses, and input/output (I/O) busses connected to peripheral devices. Such components are commonly placed on a motherboard within the computer system. To manage dataflow, a motherboard can include a chipset that acts as a traffic cop. In particular, the chipset provides controller logic that controls access to data/system, I/O busses and access to memory systems and caches. In other words, the chipset handles the general dataflow on the motherboard.
One type of chipset commonly used for systems that employ the Intel Pentium® Pro Family bus architectures is the two-part chipset referred to as Northbridge and Southbridge. Northbridge typically refers to controller circuitry that communicates with one or more of the computing system's processors and controls interaction with memory and memory caches and graphics ports. Southbridge typically refers to controller circuitry that handles I/O device functions. Each of these chipsets can be referred to as a hub for handling various functions for the motherboard.
In a multi-processor system, multiple processors must share data and system busses to access resources. Typically, to determine which processor can access a bus, a bus arbitration scheme must be implemented. A prior bus arbitration scheme is described in the Pentium® Pro Family Developer's Manual, Volume 1: Specifications, Chapter 4, at pp. 4-1-4-42, (1996) (“Pentium Pro Developer's Manual”) that is used in a prior multi-processor system using, e.g., the Northbridge and Southbridge chipsets. In this scheme, a bus agent can be a symmetrical agent or a priority agent. For a symmetrical agent, it shares access to a bus equally with other symmetrical bus agents, e.g., using a round-robin algorithm. A priority agent, however, will be granted access to a bus over a symmetrical agent. Processors are considered symmetrical agents and I/O devices or memory systems are considered priority agents.
Such a prior bus arbitration scheme has a number of limitations. For instance, in a multi-processor system, a special type of processor is required with built-in arbitration logic to implement the bus arbitration protocol. Furthermore, in the case where the multiple processors are considered symmetrical agents, the prior bus arbitration scheme is fixed and each processor has equal share of a bus, regardless of processor type or operation being performed. As a result, this scheme lacks flexibility for changing utilization of a bus among different types of processors from a policy point of view. In addition, this scheme cannot take into account different bus utilization models and information. For example, in the event when one processor may have a higher demand for a bus over another processor, granting bus utilization equally among the processors disadvantages the higher demand processor. The inflexibility of the bus utilization scheme can severely degrade system performance. Moreover, the prior chipset also required a system reset when processor configurations changed in the system and that all processors be synchronized at all time. In addition, the bus arbitration scheme for the prior chipset was limited to a maximum of four processors on the motherboard and not expandable for computing systems requiring more than four processors.
Thus, what is needed is an improved bus arbitration scheme that is flexible for changes to bus utilization in a computing system (without requiring special multi-processors). Additionally, improved chipsets are needed that are scalable and provide smooth system transitions in the case of processor configuration changes.